Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture

In deep-submicron era, wire delay is becoming a bottleneck while pursuing even higher system clock speed. Several distributed register (DR) architectures have been proposed to cope with this problem by keeping most wires local. In this article, we propose a new resourceconstrained communication synthesis algorithm for optimizing both interisland connections (IICs) and latency targeting on distributed registerfile microarchitecture (DRFM). The experimental results show that up to 24.7% and 12.7% reduction on IIC and latency can be achieved respectively as compared to the previous work. key words: communication synthesis, distributed register-file microarchitecture, interconnect minimization, resource binding, scheduling